SSRP

Hardware
MAX5190 DAC board
LTC1746 ADC board
USB 2.0 interface board
I/O test board

Software
Firmware
GNU Radio integration

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USB 2.0 interface board
Connectivity for the SSRP is provided by a USB 2.0 (480Mbps) interface board based on the Cypress Semiconductor CY7C68013 EZ-USB FX2. This board is an off the self part available from ELRASoft for $89. The FX2 is well suited for high speed data transfers; the chip itself supports the full 480Mbps USB 2.0 bandwidth and provides a versatile FIFO-buffered 16bit parallel data interface. The ELRASoft board provides easy access to this bus and most of the other FX2 signals on a standard 40pin header.

Cypress EZ-USB FX2 Datasheet
Cypress EZ-USB FX Technical Reference Manual

Header pinout
NOTE: Pin 1 is furthest from the USB connector.

Pin	Name	Type	Description
1	GND	Ground
2	Vcc	Power	3.3V max 0.3A
3	SDA	Open Drain	Data for I2C compatible interface ,2.2k pull-up resistor is connected to Vcc
4	SCL	Open Drain	Clock for I2C compatible interface ,2.2k pull-up resistor is connected to Vcc
5	IFCLK	I/O/Z	Interface Clock. use for synchronously clocking data into or out of the slave FIFOs
6	CTL0/FLAGA	Output	GPIF control Output; Programmable slave-FIFO output status flag signal
7	CTL1/FLAGB	Output	GPIF control Output; Programmable slave-FIFO output status flag signal
8	CTL2/FLAGC	Output	GPIF control Output; Programmable slave-FIFO output status flag signal
9	PA0/INT0	I/O/Z	Bidirectional I/O port A pin; Active-low 8051 interrupt input signal
10	PA1/INT1	I/O/Z	Bidirectional I/O port A pin; Active-low 8051 interrupt input signal
11	PA2/SLOE	I/O/Z	Bidirectional I/O port A pin; Output enable for the slave FIFO connected to FD[0-15]
12	PA3/WU2	I/O/Z	Bidirectional I/O port A pin; USB wake up
13	PA4/FIFOADR0	I/O/Z	Bidirectional I/O port A pin; Address select for the slave FIFO connected to FD[0-15]
14	PA5/FIFOADR1	I/O/Z	Bidirectional I/O port A pin; Address select for the slave FIFO connected to FD[0-15]
15	PA6/PKTEND	I/O/Z	Bidirectional I/O port A pin; Packet end for the slave FIFO connected to FD[0-7/15]
16	PA7/FLAGD/SLCS	I/O/Z	Bidirectional I/O port A pin; Slave FIFO enable or output status flag signal
17	RESET	Input	Active low reset. Resets entire chip
18	WAKEUP	Input	USB wake up, starts oscillator, interrupts and exits the suspend mode
19	GND	Power
20	PB0/FD0	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
21	PB1/FD1	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
22	PB2/FD2	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
23	PB3/FD3	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
24	PB4/FD4	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
25	PB5/FD5	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
26	PB6/FD6	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
27	PB7/FD7	I/O/Z	Bidirectional I/O port B pin; Bidirectional FIFO/GPIF data bus
28	PD0/FD8	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
29	PD1/FD9	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
30	PD2/FD10	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
31	PD3/FD11	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
32	PD4/FD12	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
33	PD5/FD13	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
34	PD6/FD14	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
35	PD7/FD15	I/O/Z	Bidirectional I/O port D pin; Bidirectional FIFO/GPIF data bus
36	CLKOUT	O/Z	12-24-48 MHz clock, phase locked to the 24MHz input clock
37	RDY0/SLRD	Input	GPIF input signal; Read strobe for the slave FIFOs connected to FD[0-7/15]
38	RDY1/SLWR	Input	GPIF input signal; Write strobe for the slave FIFOs connected to FD[0-7/15]
39	GND	Ground
40	USB5	Power	5V max 0.3A