SSRP
Overview
Project Status
Hardware
MAX5190 DAC board
LTC1746 ADC board
USB 2.0 interface board
I/O test board
Software
Firmware
GNU Radio integration
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LTC1746 14bit 25Msps ADC board

Schematic

Board Layout

Blank PCB

Assembled Board


LTC1746 User Manual V0.1 (PDF)
LTC1746 Assembly Manual V0.1 (PDF)

LTC1746 board design files Revision 1C (This files are the production LTC1746)
(Gerber files, Cadsoft Eagle Cad drawings)The LTC1746 board is being developed as the first functional daughterboard for the SSRP. This board provides medium dynamic range (14 bits, ~96dB SFDR) and a high sampling rate (20+Msps). The Rev. 0 design has been produced and is currently undergoing performance characterization tests.

A brief list of specifications and a functional overview can be found below:

Specifications
Resolution14 bits
Sample Rate25Msps max (set by crystal)
Analog inputBi-polar, Single-ended
Analog input impedance50 ohms
Analog input voltage+-1.6V
SNR77.5dB
SFDR91dB
Physicalapprox. 2"x2"

Linear Technology LTC1746 Datasheet
Texas Instruments THS4501 Datasheet
National Semiconductor LP2989 Datasheet

Production/Purchasing information
As of 10/14/2007 I have one LTC1746 assembled board available. I also have a few blank PCBs that I will sell separately or with the three ICs pre-installed. The assembled board is $120. Bare PCBs with documentation are $15. PCBs with the LTC1746, LP2989 and THS4501 installed are $60.

Functional Overview
(Please note that suggestions and design change recommendations are quite welcome.)

The analog input stage is loosely based on Figure 102 in the THS4501 datasheet. A single incoming bi-polar analog input is buffered and converted to differential by a Texas Instruments THS4501 differential amplifier configured for unity gain. The output of this amplifier is lowpass filtered and drives the differential ADC inputs using an RC network described in Figure 4 of the LTC1746 datasheet (note that the LT1810 stage is replaced by the THS4501 above).

The convert clock is supplied by a fixed frequency crystal oscillator. Currently the oscillator drives the converter directly in single-ended mode for design simplicity. This design choice is not optimal for higher sampling rates because it is more susceptible to noise (resulting in jitter) than differential drive. Performance analysis of the Rev. 0 board will determine whether the additional complexity of differential clock drive is justified in subsequent revisions. It is likely that "production" revisions will also provide an external input for a user-supplied conversion clock. The conversion clock frequency is determined by the bandwidth available from the host machine USB controller. A sampling rate of 1 Msps requires a sustained transfer rate of 2 MB/s. Currently the Intel ICH4 controller used for development can sustain transfers in the 40MB/s range.

The board utilizes two supply nets, 5V for the analog input buffer, the ADC analog section and the conversion clock; 3.3V supplies the ADC digital output. An external supply provides 6-13V to a National Semiconductor LP2989 5V linear regulator. The LP2989 has good supply rejection and low internal noise to provide clean power for the analog circuitry. The 3.3V supply comes directly from the USB interface board.

The ADC outputs are connected directly to the USB interface board parallel data bus. There is a chance that an additional latch/buffer might be needed between the outputs and the bus if digital switching currents significantly degrade analog performance. The integral current limiting resistors in the ADC and efforts to minimize output trace capacitance will hopefully mitigate this possibility.

(C) David Carr 2004-2005